The design of central processing units (CPU) has typically included multiple functional units, such as floating point and integer processor units. Historically, the computer instructions have been organized and distributed to only one functional unit in any one instruction issue cycle. Horizontally multiprogrammed CPUs permit simultaneous and parallel operation of more than one functional unit every instruction issue cycle.
To provide simultaneous operation of multiple function units, the width of the instruction word increases to accommodate the multiple instruction components. However, as programs are unlikely to contain the operations necessary to maintain each functional unit busy for every execution cycle, the widened instruction stream will likely contain no-ops for most of the functional units.
While a variable length encoding of the instructions would address the problem of no-ops, the variable length encoding in high performance (pipelined) architectures increases the complexity of page-faults when the instructions are allowed to cross page boundaries, and the overall instruction cycle time may be adversely affected by the determination of the length of the current instruction so as to advance the program counter and initiate the next instruction cache.
Furthermore, the instruction stream parsing complexity may require the introduction of an additional pipeline stage to allow proper determination that an entire instruction is available for dispatch, and that an instruction pipeline stage may be introduced to ease the problem of read-ahead, which itself may result in additional page-fault complexities and latency in the presence of a taken branch instruction. Therefore, the general concept of variable length instruction encoding provides only limited enhancement of the efficiency of horizontally multiprogrammed machines, and also tends to self-limit as actual programs are executed by the multiple functional units.